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ICS9LPR502 idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 56-pin ck505 w/fully integrated voltage regulator 1 datasheet recommended application: key specifications: ck505 compliant clock with fully integrated voltage regulator, pcie gen 1 compliant ? cpu outputs cycle-cycle jitter < 85ps src output cycle-cycle jitter < 125ps pci outputs cycle-cycle jitter < 250ps +/- 100ppm frequency accuracy on cpu & src clocks pin configuration output features: 2 - cpu differential low power push-pull pairs 7 - src differential low power push-pull pairs 1 - cpu/src selectable differential low power push-pull pair 1 - src/dot selectable differential low power push-pull pair 5 - pci, 33mhz 1 - pci_f, 33mhz free running 1 - usb, 48mhz 1 - ref, 14.318mhz features/benefits: does not require external pass transistor for voltage regulator supports spread spectrum modulation, default is 0.5% down spread uses external 14.318mhz crystal, external crystal load caps are required for frequency tuning one differential push-pull pair selectable between src and two single-ended outputs table 1: cpu frequency select table pci0/cr#_a 1 56 sclk vddpci 2 55 sdata pci1/cr#_b 3 54 ref0/fslc/test_sel pci2/tme 4 53 vddref pci3 5 52 x1 pci4/src5_en 6 51 x2 pci_f5/itp_en 7 50 gndref gndpci 8 49 fslb/test_mode vdd48 9 48 ck_pwrgd/pd# usb_48mhz/fsla 10 47 vddcpu gnd4811 46cput0 vddi/o96mhz 12 45 cpuc0 dott_96/srct0 13 44 gndcpu dotc_96/srcc0 14 43 cput1 gnd 15 42 cpuc1 vdd 16 41 vddi/ocpu srct1/se1 17 40 nc srcc1/se218 39cput2_itp/srct8 gnd 19 38 cpuc2_itp/srcc8 vddpll3i/o 20 37 vddsrci/o srct2/satat 21 36 srct7/cr#_f srcc2/satac 22 35 srcc7/cr#_e gndsrc 23 34 gndsrc srct3/cr#_c 24 33 srct6 srcc3/cr#_d 25 32 srcc6 vddsrci/o 26 31 vddsrc srct4 27 30 pci_stop#/srct5 srcc4 28 29 cpu_stop#/srcc5 56-ssop/tssop ics 9lpr502 fs l c 2 b0b7 fs l b 1 b0b6 fs l a 1 b0b5 cpu mhz src mhz pci mhz ref mhz u sb mhz dot mhz 0 0 0 266.66 0 0 1 133.33 0 1 0 200.00 0 1 1 166.66 1 0 0 333.33 1 0 1 100.00 1 1 0 400.00 111 1. fs l a and fs l b are low-threshold inputs.please see v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. also refer to the test clarification table. 2. fs l c is a three-level input. please see the v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. reserved 100.00 33.33 14.318 48.00 96.00
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 2 datasheet ssop/tssop pin description pin # pin name type description 1 pci0/cr#_a i/o 3.3v pci clock output or clock request control a for either src0 or src2 pair the power-up default is pci0 output, but this pin may also be used as a clock request control of src pair 0 or src pair 2 via smbus. before configuring this pin as a clock request pin, the pci output must first be disabled in byte 2, bit 0 of smbus address space . after the pci output is disabled (high-z), the pin can then be set to serve as a clock request pin for either src pair 2 or pair 0 using the cr#_a_en bit located in byte 5 of smbus address space. byte 5, bit 7 0 = pci0 enabled (default) 1= cr#_a enabled. byte 5, bit 6 controls whether cr#_a controls src0 or src2 pair byte 5, bit 6 0 = cr#_a controls src0 pair (default), 1= cr#_a controls src2 pair 2 vddpci pwr power supply pin for the pci outputs, 3.3v nominal 3 pci1/cr#_b i/o 3.3v pci clock output/clock request control b for either src1 or src4 pair the power-up default is pci1 output, but this pin may also be used as a clock request control of src pair 1 or src pair 4 via smbus. before configuring this pin as a clock request pin, the pci output must first be disabled in byte 2, bit 1 of smbus address space . after the pci output is disabled (high-z), the pin can then be set to serve as a clock request pin for either src pair 1 or pair 4 using the cr#_b_en bit located in byte 5 of smbus address space. byte 5, bit 5 0 = pci1 enabled (default) 1= cr#_b enabled. byte 5, bit 6 controls whether cr#_b controls src1 or src4 pair byte 5, bit 4 0 = cr#_b controls src1 pair (default) 1= cr#_b controls src4 pair 4pci2/tme i/o 3.3v pci clock output / trusted mode enable (tme) latched input. this pin is sampled on power- up as follows 0 = overclocking of cpu and src allowed 1 = overclocking of cpu and src not allowed after being sampled on power-up, this pin becomes a 3.3v pci output 5 pci3 out 3.3v pci clock output. 6 pci4/src5_en i/o 3.3v pci clock output / src5 pair or pci_stop#/cpu_stop# enable strap. on powerup, the logic value on this pin determines if the src5 pair is enabled or if cpu_stop#/pci_stop# is enabled (pins 29 and 30). the latched value controls the pin function on pins 29 and 30 as follows 0 = pci_stop#/cpu_stop# 1 = src5/src5# 7 pci_f5/itp_en i/o free running pci clock output and itp/src8 enable strap. this output is not affected by the state of the pci_stop# pin. on powerup, the state of this pin determines whether pins 38 and 39 are an itp or src pair. 0 =src8/src8# 1 = itp/itp# 8 gndpci pwr ground for pci clo cks. 9 vdd48 pwr power supply for usb clock, nominal 3.3v. 10 usb_48mhz/fsla i/o fixed 48mhz usb clock output. 3.3v./ 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. 11 gnd48 pwr ground pin for the 48mhz outputs. 12 vdd96_io pwr power supply for dot96 output. 1.05 to 3.3v +/-5%. 13 dott_96/srct0 out true clock of src or dot96. the power-up default function is src0. after powerup, this pin function may be changed to dot96 via smbus byte 1, bit 7 as follows: 0= src0 1=dot96 14 dotc_96/srcc0 out complement clock of src or dot96. the power-up default function is src0#. after powerup, this pin function may be changed to dot96# via smbus byte 1, bit 7 as follows 0= src0# 1=dot96# 15 gnd pwr ground pin for the dot96 clocks. 16 vdd pwr power supply for src / se1 and se2 clo cks, 3.3v nominal.
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 3 datasheet ssop/tssop pin description (continued) pin # pin name type description 17 srct1/se1 out true clock of differential src1 clock pair / 3.3v single-ended output. the powerup default is 100 mhz src, -0.5% downspread. the pin function may be changed via smbus b1b[4:1] 18 srcc1/se2 out complement clock of differential src1 clock pair / 3.3v single-ended output. the powerup default is 100 mhz src, -0.5% downspread. the pin function may be changed via smbus b1b[4:1] 19 gnd pwr ground pin for src / se1 and se2 clo cks, pll3. 20 vddpll3_io pwr power supply for pll3 output. 1.05 to 3.3v +/-5%. 21 srct2/satat out true clock of differential src/sata clock pair. 22 srcc2/satac out complement clock of differential src/sata clock pair. 23 gndsrc pwr ground pin for src clocks. 24 srct3/cr#_c i/o true clock of differential src clock pair/ clock request control c for either src0 or src2 pair the power-up default is srcclk3 output, but this pin may also be used as a clock request control of src pair 0 or src pair 2 via smbus. before configuring this pin as a clock request pin, the src3 output must first be disabled in byte 4, bit 7 of smbus address space . after the src3 output is disabled, the pin can then be set to serve as a clock request pin for either src pair 2 or pair 0 using the cr#_c_en bit located in byte 5 of smbus address space. byte 5, bit 3 0 = src3 enabled (default) 1= cr#_c enabled. byte 5, bit 2 controls whether cr#_c controls src0 or src2 pair byte 5, bit 2 0 = cr#_c controls src0 pair (default), 1= cr#_c controls src2 pair 25 srcc3/cr#_d i/o complementary clock of differential src clock pair/ clock request control d for either src1 or src4 pair the power-up default is srcclk3 output, but this pin may also be used as a clock request control of src pair 1 or src pair 4 via smbus. before configuring this pin as a clock request pin, the src3 output must first be disabled in byte 4, bit 7 of smbus address space . after the src3 output is disabled, the pin can then be set to serve as a clock request pin for either src pair 1 or pair 4 using the cr#_d_en bit located in byte 5 of smbus address space. byte 5, bit 1 0 = src3 enabled (default) 1= cr#_d enabled. byte 5, bit 0 controls whether cr#_d controls src1 or src4 pair byte 5, bit 0 0 = cr#_d controls src1 pair (default), 1= cr#_d controls src4 pair 26 vddsrc_io pwr power supply for src clocks. 1.05 to 3.3v +/-5%. 27 srct4 i/o true clock of differential src clock pair 4 28 srcc4 i/o complement clock of differential src clock pair 4
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 4 datasheet ssop/tssop pin description (continued) pin # pin name type description 29 cpu_stop#/srcc5 i/o stops all cpu clocks, except those set to be free running clo cks / complement clock of differential src pair. the func tion of this pin is set up by the power-up strap on pin 6, pci4/src5_en. the logic value sampled on pin 6 at power-up sets the function as follows: 0= cpu_stop# 1 = src5 in amt mode 3 bits are shifted in from the ich to set the fsc, fsb, fsa values 30 pci_stop#/srct5 i/o stops all pci clocks, except those set to be free running clocks / complement clock of differential src pair. the func tion of this pin is set up by the power-up strap on pin 6, pci4/src5_en. the logic value sampled on pin 6 at power-up sets the function as follows: 0= pci_stop# 1 = src5# in amt mode, this pin is a clock input which times the fsc, fsb, fsa bits shifted in on pin 37. 31 vddsrc pwr vdd pin for src pre-drivers, 3.3v nominal 32 srcc6 out complement clock of low power differential src clock pair. 33 srct6 out true clock of low power differential src clock pair. 34 gndsrc pwr ground for src clocks 35 srcc7/cr#_e i/o src7 complement or clock request control e for src6 pair the power-up default is src7#, but this pin may also be used as a clock request control of src6 via smbus. before configuring this pin as a clock request pin, the src7 output pair must first be disabled in byte 3, bit 3 of smbus configuration space . after the src output is disabled (high-z), the pin can then be set to serve as a clock request for src6 pair using byte 6, bit 7 of smbus configuration space byte 6, bit 7 0 = src7# enabled (default) 1= cr#_e controls src6. 36 srct7/cr#_f i/o src7 true or clock request control 8 for src8 pair the power-up default is src7, but this pin may also be used as a clock request control of src8 via smbus. before configuring this pin as a clock request pin, the src7 output pair must first be disabled in byte 3, bit 3 of smbus configuration space after the src output is disabled (high-z), the pin can then be set to serve as a clock request for src8 pair using byte 6, bit 6 of smbus configuration space byte 6, bit 6 0 = src7# enabled (default) 1 = cr#_f controls src8. 37 vddsrc_io pwr power supply for src outputs. 1.05 to 3.3v +/-5%. 38 cpuc2_itp/srcc8 out complement clock of low power differential cpu2 /complement clock of differential src pair. the function of this pin is determined by the latched input value on pin 7, pcif5/itp_en on powerup. the function is as follows: pin 7 latched input value 0 = src8# 1 = itp# 39 cput2_itp/srct8 out true clock of low power differential cpu2/true clock of differential src pair. the function of this pin is determined by the latched input value on pin 7, pcif5/itp_en on powerup. the function is as follows: pin 7 latched input value 0 = src8 1 = itp 40 nc n/a no connect 41 vddcpu_io pwr supply for cpu outputs. 1.05 to 3.3v +/-5%. 42 cpuc1_f out complement clock of low power differenatial cpu clock pair. this clock w ill be free-r unning during iamt. 43 cput1_f out true clock of low power differential cpu clock pair. this clock will be free-running during iamt. 44 gndcpu pwr ground pin for cpu outputs 45 cpuc0 out complement clock of low power differential cpu clock pair. 46 cput0 out true clock of low power differential cpu clock pair. 47 vddcpu pwr power supply 3.3v nominal.
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 5 datasheet ssop/tssop pin description (continued) fully integrated regulator connection for desktop/mobile applications pin # pin name type description 48 ck_pwrgd/pd# in notifies ck505 to sample latched inputs, or iamt entry/exit, or pwrdwn# mode 49 fslb/test_mode in 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. test_mode is a real time input to select between hi-z and ref/n divider mode while in test mode. refer to test clarification table. 50 gndref pwr gr ound pin for crystal oscillator circuit 51 x2 out crystal output, nominally 14.318mhz. 52 x1 in crystal input, nominally 14.318mhz. 53 vddref pwr power pin for the ref outputs, 3.3v nominal. 54 ref0/fslc/test_sel i/o 3.3v 14.318mhz reference clock/3.3v tolerant low threshold input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values/ test_sel: 3-level latched input to enable test mode. refer to test clarification table. 55 sdata i/o data pin for smbus circuitry, 5v tolerant. 56 sclk in clock pin of smbus circuitry, 5v tolerant. 1.05v to 3.3v (+/-5%) nc pin 40 cpu_io decoupling network 96_io decoupling network ICS9LPR502 ics9lprs502 vddcpu_io, pin 41 vddsrc_io pin 37, 26 vddpll3_io, pin 20 vdd96_io, pin 12 pll3_io decoupling network src_io decoupling network
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 6 datasheet gndref fslb/test_mode ck_pwrgd/pd# vddcpu cput0 cpuc0 gndcpu cput1 cpuc1 vddi/ocpu nc cput2_itp/srct8 cpuc2_itp/srcc8 vddsrci/o 56 55 54 53 52 51 50 49 48 47 46 45 44 43 x2 142 srct7/cr#_f x1 241 srcc7/cr#_e vddref 340 gndsrc ref0/fslc/test_sel 439 vddsrc sdata 538 pci_stop#/srct5 sclk 6 37 cpu_stop#/srcc5 pci0/cr#_a 736 srct11 vddpci 835 srcc11 pci1/cr#_b 934 srcc4 pci2/tme 10 33 srct4 pci3 11 32 vddsrci/o pci4/src5_en 12 31 srcc3/cr#_d pci_f5/itp_en 13 30 srct3/cr#_c gndpci 14 29 gndsrc 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vdd48 usb_48mhz/fsla gnd48 vddi/o96mhz dott_96/srct 0 dotc_96/srcc0 gnd vdd srct1/se1 srcc1/se2 gnd vddpll3i/o srct2/sata t srcc2/satac ICS9LPR502 56-pin mlf ssop/tssop pin description (continued)
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 7 datasheet mlf pin description pin # pin name type description 1 x2 out crystal output, nominally 14.318mhz. 2 x1 in crystal input, nominally 14.318mhz. 3 vddref pwr power pin for the ref outputs, 3.3v nominal. 4 ref0/fslc/test_sel i/o 3.3v 14.318mhz reference clock/3.3v tolerant low threshold input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values/ test_sel: 3-level latched input to enable test mode. refer to test clarification table. 5 sdata i/o data pin for smbus circuitry, 5v tolerant. 6 sclk in clock pin of smbus circuitry, 5v tolerant. 7 pci0/cr#_a i/o 3.3v pci clock output or clock request control a for either src0 or src2 pair the power-up default is pci0 output, but this pin may also be used as a clock request control of src pair 0 or src pair 2 via smbus. before configuring this pin as a clock request pin, the pci output must first be disabled in byte 2, bit 0 of smbus address space . after the pci output is disabled (high-z), the pin can then be set to serve as a clock request pin for either src pair 2 or pair 0 using the cr#_a_en bit located in byte 5 of smbus address space. byte 5, bit 7 0 = pci0 enabled (default) 1= cr#_a enabled. byte 5, bit 6 controls whether cr#_a controls src0 or src2 pair byte 5, bit 6 0 = cr#_a controls src0 pair (default), 1= cr#_a controls src2 pair 8 vddpci pwr power supply pin for the pci outputs, 3.3v nominal 9 pci1/cr#_b i/o 3.3v pci clock output/clock request control b for either src1 or src4 pair the power-up default is pci1 output, but this pin may also be used as a clock request control of src pair 1 or src pair 4 via smbus. before configuring this pin as a clock request pin, the pci output must first be disabled in byte 2, bit 1 of smbus address space . after the pci output is disabled (high-z), the pin can then be set to serve as a clock request pin for either src pair 1 or pair 4 using the cr#_b_en bit located in byte 5 of smbus address space. byte 5, bit 5 0 = pci1 enabled (default) 1= cr#_b enabled. byte 5, bit 6 controls whether cr#_b controls src1 or src4 pair byte 5, bit 4 0 = cr#_b controls src1 pair (default) 1= cr#_b controls src4 pair 10 pci2/tme i/o 3.3v pci clock output / trusted mode enable (tme) latched input. this pin is sampled on power-up as follows 0 = overclocking of cpu and src allowed 1 = overclocking of cpu and src not allowed after being sampled on power-up, this pin becomes a 3.3v pci output 11 pci3 out 3.3v pci clock output. 12 pci4/src5_en i/o 3.3v pci clock output / src5 pair or pci_stop#/cpu_stop# enable strap. on powerup, the logic value on this pin determines if the src5 pair is enabled or if cpu_stop#/pci_stop# is enabled (pins 29 and 30). the latched value controls the pin function on pins 29 and 30 as follows 0 = pci_stop#/cpu_stop# 1 = src5/src5# 13 pci_f5/itp_en i/o free running pci clock output and itp/src8 enable strap. this output is not affected by the state of the pci_stop# pin. on powerup, the state of this pin determines whether pins 38 and 39 are an itp or src pair. 0 =src8/src8# 1 = itp/itp# 14 gndpci pwr ground for pci clocks.
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 8 datasheet mlf pin description (continued) pin # pin name type description 15 vdd48 pwr power supply for usb clock, nominal 3.3v. 16 usb_48mhz/fsla i/o fixed 48mhz usb clock output. 3.3v./ 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. 17 gnd48 pwr ground pin for the 48mhz outputs. 18 vdd96_io pwr power supply for dot96 output. 1.05 to 3.3v +/-5%. 19 dott_96/srct0 out true clock of src or dot96. the power-up default function is src0. after powerup, this pin function may be changed to dot96 via smbus byte 1, bit 7 as follows: 0= src0 1=dot96 20 dotc_96/srcc0 out complement clock of src or dot96. the power-up default function is src0#. after powerup, this pin function may be changed to dot96# via smbus byte 1, bit 7 as follows 0= src0# 1=dot96# 21 gnd pwr ground pin for the dot96 clocks. 22 vdd pwr power supply for src / se1 and se2 clo cks, 3.3v nominal. 23 srct1/se1 out true clock of differential src1 clock pair / 3.3v single-ended output. the powerup default is 100 mhz src, -0.5% downspread. the pin function may be changed via smbus b1b[4:1] 24 srcc1/se2 out complement clock of differential src1 clock pair / 3.3v single-ended output. the powerup default is 100 mhz src, -0.5% downspread. the pin function may be changed via smbus b1b[4:1] 25 gnd pwr ground pin for src / se1 and se2 clo cks, p ll3. 26 vddpll3_io pwr power supply for pll3 output. 1.05 to 3.3v +/-5%. 27 srct2/satat out true clock of differential src/sata clock pair. 28 srcc2/satac out complement clock of differential src/sata clock pair.
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 9 datasheet mlf pin description (continued) pin # pin name type description 29 gndsrc pwr ground pin for src clocks. 30 srct3/cr#_c i/o true clock of differential src clock pair/ clock request control c for either src0 or src2 pair the power-up default is srcclk3 output, but this pin may also be used as a clock request control of src pair 0 or src pair 2 via smbus. before configuring this pin as a clock request pin, the src3 output must first be disabled in byte 4, bit 7 of smbus address space . after the src3 output is disabled, the pin can then be set to serve as a clock request pin for either src pair 2 or pair 0 using the cr#_c_en bit located in byte 5 of smbus address space. byte 5, bit 3 0 = src3 enabled (default) 1= cr#_c enabled. byte 5, bit 2 controls whether cr#_c controls src0 or src2 pair byte 5, bit 2 0 = cr#_c controls src0 pair (default), 1= cr#_c controls src2 pair 31 srcc3/cr#_d i/o complementary clock of differential src clock pair/ clock request control d for either src1 or src4 pair the power-up default is srcclk3 output, but this pin may also be used as a clock request control of src pair 1 or src pair 4 via smbus. before configuring this pin as a clock request pin, the src3 output must first be disabled in byte 4, bit 7 of smbus address space . after the src3 output is disabled, the pin can then be set to serve as a clock request pin for either src pair 1 or pair 4 using the cr#_d_en bit located in byte 5 of smbus address space. byte 5, bit 1 0 = src3 enabled (default) 1= cr#_d enabled. byte 5, bit 0 controls whether cr#_d controls src1 or src4 pair byte 5, bit 0 0 = cr#_d controls src1 pair (default), 1= cr#_d controls src4 pair 32 vddsrc_io pwr power supply for src outputs. 1.05 to 3.3v +/-5%. 33 srct4 i/o true clock of differential src clock pair 4 34 srcc4 i/o complement clock of differential src clock pair 4 35 srcc11 out complement clock of low power differential src clock pair. 36 srct11 out true clock of low power differential src clock pair. 37 cpu_stop#/srcc5 i/o stops all cpu clocks, except those set to be free r unning clo cks / complement clock of differential src pair. the function of this pin is set up by the power-up strap on pin 6, pci4/src5_en. the logic value sampled on pin 6 at power-up sets the function as follows: 0= cpu_stop# 1 = src5 in amt mode 3 bits are shifted in from the ich to set the fsc, fsb, fsa values 38 pci_stop#/srct5 i/o stops all pci clocks, except those set to be free running clo cks / complement clock of differential src pair. the function of this pin is set up by the power-up strap on pin 6, pci4/src5_en. the logic value sampled on pin 6 at power-up sets the function as follows: 0= pci_stop# 1 = src5# in amt mode, this pin is a clock input which times the fsc, fsb, fsa bits shifted in on pin 37. 39 vddsrc pwr vdd pin for src pre-drivers, 3.3v nominal 40 gndsrc pwr ground for src clocks 41 srcc7/cr#_e i/o src7 complement or clock request control e for src6 pair the power-up default is src7#, but this pin may also be used as a clock request control of src6 via smbus. before configuring this pin as a clock request pin, the src7 output pair must first be disabled in byte 3, bit 3 of smbus configuration space . after the src output is disabled (high-z), the pin can then be set to serve as a clock request for src6 pair using byte 6, bit 7 of smbus configuration space byte 6, bit 7 0 = src7# enabled (default) 1= cr#_e controls src6. 42 srct7/cr#_f i/o src7 true or clock request control 8 for src8 pair the power-up default is src7, but this pin may also be used as a clock request control of src8 via smbus. before configuring this pin as a clock request pin, the src7 output pair must first be disabled in byte 3, bit 3 of smbus configuration space after the src output is disabled (high-z), the pin can then be set to serve as a clock request for src8 pair using byte 6, bit 6 of smbus configuration space byte 6, bit 6 0 = src7# enabled (default) 1 = cr#_f controls src8.
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 10 datasheet mlf pin description (continued) pin # pin name type description 43 vddsrc_io pwr power supply for src outputs. 1.05 to 3.3v +/-5%. 44 cpuc2_itp/srcc8 out complement clock of low power differential cpu2/complement clock of differential src pair. the function of this pin is determined by the latched input value on pin 7, pcif5/itp_en on powerup. the function is as follows: pin 7 latched input value 0 = src8# 1 = itp# 45 cput2_itp/srct8 out true clock of low power differential cpu2/true clock of differential src pair. the function of this pin is determined by the latched input value on pin 7, pcif5/itp_en on powerup. the function is as follows: pin 7 latched input value 0 = src8 1 = itp 46 nc nc not connected 47 vddcpu_io pwr power supply for cpu outputs. 1.05 to 3.3v +/-5%. 48 cpuc1_f out complement clock of low power differenatial cpu clock pair. this clock will be free-running during iamt. 49 cput1_f out true clock of low power differential cpu clock pair. this clock will be free-running during iamt. 50 gndcpu pwr ground pin for cpu outputs 51 cpuc0 out complement clock of low power differential cpu clock pair. 52 cput0 out true clock of low power differential cpu clock pair. 53 vddcpu pwr power supply 3.3v nominal. 54 ck_pwrgd/pd# in notifies ck505 to sample latched inputs, or iamt entry/exit, or pwrdwn# mode 55 fslb/test_mode in 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. test_mode is a real time input to select between hi-z and ref/n divider mode while in test mode. refer to test clarification table. 56 gndref pwr ground pin for crystal oscillator circuit
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 11 datasheet funtional block diagram power groups general description ICS9LPR502 follows intel ck505 yellow cover specification. this clock synthesizer provides a single chip solution for next generation intel processors and intel chipsets. ICS9LPR502 is driven with a 14.318mhz crystal. it also provides a tight ppm accuracy output for serial ata and pci-express support. ref cpu(1:0) cpu pll1 ss osc ref src(7:3) pll2 non-ss pll3 ss 7 src8/itp pci(5:0) src2/sata src1/se(2:1) se outputs s ata dot96mhz pci33mhz src src s r c _ m a i n pci33mhz differential output src0/dot96 48mhz 48mhz cpu fsla ckpwrgd/pd# pci_stop# cpu_stop# cr#_(a:f) src5_en itp_en fslc/testsel fslb/testmode control logic x1 x2 vdd gnd 41 44 cpuclk low power outputs 47 44 26, 37 23,34 low power outputs 31 23,34 pll 1 20 19 low power outputs 16 19 pll 3 12 11 dot 96mhz low power outputs 911 53 50 28 usb 48 xtal, ref pciclk srcclk pin number description pll3/se master clock, analog
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 12 datasheet absolute maximum ratings - dc parameters parameter symbol conditions min max units notes maximum supply voltage vddxxx supply voltage 4.6 v 7 maximum supply voltage vddxxx_io low-voltage differential i/o supply 3.8 v 7 maximum input voltage v ih 3.3v inputs 4.6 v 4,5,7 minimum input voltage v il any input gnd - 0.5 v 4,7 storage temperature ts - -65 150 c 4,7 input esd protection esd prot human body model 2000 v 6,7 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied, nor guaranteed. 3 maximum input voltage is not to exceed vdd electrical characteristics - input/supply/common output dc parameters parameter symbol conditions min max units notes ambient o p eratin g tem p tambient - 0 70 c su pp l y volta g evddxxx su pp l y volta g e 3.135 3.465 v su pp l y volta g e vddxxx_io low-volta g e differential i/o su pp l y 0.9975 3.465 v 10 input high voltage v ihse single-ended 3.3v inputs 2 v dd + 0.3 v3 input low voltage v ilse single-ended 3.3v inputs v ss - 0.3 0.8 v 3 low threshold input- high voltage v ih_fs_test 3.3 v +/-5% 2 vdd + 0.3 v 8 low threshold input- fsc = '1' voltage v ih_fs_fsc 3.3 v +/-5% 0.7 1.5 v 8 low threshold input- fsa,fsb = '1' voltage v ih_fs_fsab 3.3 v +/-5% 0.7 vdd+0.3 v low threshold input-low voltage v il_fs 3.3 v +/-5% v ss - 0.3 0.35 v pci3/cfg0 input v il_cfghi optional input, 2.75v typ. 2.4 vdd+0.3 v 9 pci3/cfg0 input v il_cfgmid optional input, 1.65v typ. 1.3 2 v 9 pci3/cfg0 input v il_cfglo optional input, 0.55v typ. v ss - 0.3 0.9 v 9 input leakage current i in v in = v dd , v in = gnd -5 5 ua 2 input leakage current i inres inputs with pull up or pull down resistors v in = v dd , v in = gnd -200 200 ua output high voltage v ohse single-ended outputs, i oh = -1ma 2.4 v 1 output low voltage v olse single-ended outputs, i ol = 1 ma 0.4 v 1 i ddop3.3 full active, c l = full load; idd 3.3v 200 ma i ddopio full active, c l = full load; idd io 70 ma 10 i ddiamt3.3 m1 mode, 3.3v rail 80 ma i ddiamtio m1 mode, io rail 10 ma i ddpd3.3 power down mode, 3.3v rail 5 ma i ddpdio power down mode, io rail 0.1 ma 10 input frequency f i v dd = 3.3 v 15 mhz pin inductance l p in 7nh c in logic inputs 1.5 5 pf c out output pin capacitance 6 pf c inx x1 & x2 pins 6 pf clk stabilization t stab from vdd power-up or de-assertion of pd to 1st clock 1.8 ms tdrive_cr_off t drcroff output stop after cr deasserted 400 ns tdrive_cr_on t drcron output run after cr asserted 0 us tdrive_cpu t drsrc cpu output enable after pci_stop# de-assertion 10 ns tfall_se t fall 10 ns trise_se t rise 10 ns smbus voltage v dd 2.7 5.5 v low-level output voltage v olsmb @ i pullup 0.4 v current sinking at v olsmb = 0.4 v i pullup smb data pin 4 ma sclk/sdata clock/data rise time t ri2c (max vil - 0.15) to ( min vih + 0.15 ) 1000 ns sclk/sdata clock/data fall time t fi2c (min vih + 0.15) to ( max vil - 0.15 ) 300 ns maximum smbus operating frequency f smbus 100 khz spread spectrum modulation frequency f ssmod triangular modulation 30 33 khz 1 si g nal is re q uired to be monotonic in this re g ion. 2 in p ut leaka g e current does not include in p uts with p ull-u p or p ull-down resistors 4 intentionall y blank 7 o p eration under these conditions is neither im p lied, nor g uaranteed. 8 fre q uenc y select p ins which have tri-level in p ut 9 pci3/cfg0 is o p tional 10 if p resent. not all p arts have this feature. input capacitance powerdown current electrical characteristics - input/supply/common output dc parametersdc parameters: (unless otherwise noted, guaranteed by desi gn and characterization, not 100% tested in production). 5 maximum vih is not to exceed vdd 6 human body model 3 3.3v referenced inputs are: pci_stop#, cpu_stop#, tme, src5_en, itp_en, sclkl, sdata, testmode, testsel, ckpwrgd and cr# inputs if selected. fall/rise time of all 3.3v control inputs from 20-80% iamt mode current operating supply current
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 13 datasheet ac electrical characteristics - low power differential outputs parameter symbol conditions min max units notes rising edge slew rate tslr averaging on 2.5 4 v/ns 2, 3 falling edge slew rate tflr averaging on 2.5 4 v/ns 2, 3 slew rate variation tslvar averaging on 20 % 1, 10 differential voltage swing vswing averaging off 300 mv 2 crossing point voltage vxabs averaging off 300 550 mv 1,4,5 crossing point variation vxabsvar averaging off 140 mv 1,4,9 maximum output voltage vhigh averaging off 1150 mv 1,7 minimum output voltage vlow averaging off -300 mv 1,8 duty cycle dcyc averaging on 45 55 % 2 cpu skew cpuskew averaging on 100 ps cpu[1:0] skew cpuskew10 differential measurement 100 ps 1 cpu[2_itp:0] skew cpuskew20 differential measurement 150 ps 1 src[10:0] skew srcskew differential measurement 3000 ps 1,6,11 1 measurement taken for single ended waveform on a component test board (not in system) 2 measurement taken from differential waveform on a component test board. (not in system) 3 slew rate emastured through v_swing voltage range centered about differential zero 4 vcross is defined at the voltage where clock = clock#, measured on a component test board (not in system) 6 total distributed intentional src to src skew. pcie gen2 outputs (src3, 4, 6 and 7) will have 0 nominal skew. maximum allowa ble interpair skew is 150 ps. 7 the max voltage including overshoot. 8 the min voltage including undershoot. 10 matching applies to rising edge rate for clock and falling edge rate for clock#. it is measured using a +/-75mv window center ed on the average cross point where clock rising meets c notes on dif output ac specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production ). 11 for pcie gen2 compliant devices, src 3, 4, 6, and 7 will have 0 ps nominal skew. 9 the total variation of all vcross measurements in any particular system. note this is a subset of v_cross min/mas (v_cross ab solute) allowed. the intent is to limit vcross induced cc 5 only applies to the differential rising edge (clock rising, clock# falling) clock jitter specs - low power differential outputs parameter symbol conditions min max units notes cpu jitter - cycle to cycle cpujc2c differential measurement 85 ps 1 src jitter - cycle to cycle srcjc2c differential measurement 125 ps 1,2 dot jitter - cycle to cycle dotjc2c differential measurement 250 ps 1 1 jitter specs are specified as measured on a clock characterization board. system designers need to take special care not to us e these numbers, as the in-system performance will be somewhat degraded. the receiver emts (chispet or cpu) will have the rece 2 phase jitter requirement: the deisgnated g e2 outputs will meet the reference clock jitter requiremernts from the p c i express g en2 base s pec. the test is performed on a componnet test board under quiet condittions with all outputs on. jitter analysis is performed using a standardized tool provided by the pci sig or equivalent. measurement methodology is as defined b y the pci sig. notes on dif output jitter: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 14 datasheet intentional pci clock to clock delay 200 ps nominal steps pci0 pci1 pci2 pci3 pci4 pci_f5 1.0ns electrical characteristics - pciclk/pciclk_f parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 1,2 33.33mhz output no spread 29.99700 30.00300 ns 2 33.33mhz output spread 30.08421 30.23459 ns 2 33.33mhz output no spread 29.49700 30.50300 ns 2 33.33mhz output nominal/spread 29.56617 30.58421 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.55 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 4 v/ns 1 pin to pin skew t skew v t = 1.5 v 250 ps 2 intential pci to pci delay t skew v t = 1.5 v 100 200 ps 2 duty cycle d t1 v t = 1.5 v 45 55 % 2 jitter, cycle to cycle t j c y c-c y c v t = 1.5 v 500 ps 2 t abs absolute min/max period output high current i oh output low current i ol clock period t period electrical characteristics - usb48mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 2,4 clock period t p eriod 48.00mhz output nominal 20.83125 20.83542 ns 2,3 absolute min/max period t abs 48.00mhz output nominal 20.48125 21.18542 ns 2 clk high time t hi gh 8.216563 11.15198 v clk low time t low 7.816563 10.95198 v output high voltage v oh i oh = -1 ma 2.4 v output low voltage v ol i ol = 1 ma 0.55 v v oh @min = 1.0 v -29 ma v oh @max = 3.135 v -23 ma v ol @ min = 1.95 v 29 ma v ol @ max = 0.4 v 27 ma rising edge slew rate t slr measured from 0.8 to 2.0 v 1 2 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 2 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 2 jitter, cycle to cycle t j c y c-c y c v t = 1.5 v 350 ps 2 output high current i oh output low current i ol
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 15 datasheet electrical characteristics - ref-14.318mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 2, 4 clock period tperiod 14.318mhz output nominal 69.82033 69.86224 ns 2, 3 absolute min/max period tabs 14.318mhz output nominal 69.83400 70.84800 ns 2 clk high time thigh 29.97543 38.46654 v clk low time tlow 29.57543 38.26654 v output high voltage voh ioh = -1 ma 2.4 v output low voltage vol iol = 1 ma 0.4 v output high current ioh voh @min = 1.0 v, voh@max = 3.135 v -33 -33 ma output low current iol vol @min = 1.95 v, vol @max = 0.4 v 30 38 ma rising edge slew rate tslr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate tflr measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle dt1 vt = 1.5 v 45 55 % 2 jitter, cycle to cycle tjcyc-cyc vt = 1.5 v 1000 ps 2 1 edge rate in system is measured from 0.8v to 2.0v. 2 duty cycle, peroid and jitter are measured with respect to 1.5v 3 the average period over any 1us period of time 4 using frequency counter with the measurment interval equal or greater that 0.15s, target frequencies are 14.318180 mhz, 33.3333 33mhz and 48.000000mhz notes on se outputs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 16 datasheet pin 17 pin 18 spread mhz mhz % 000 0 0 0 0 1 100.00 100.00 0.5% down spread srcclk1 from src_main 0 0 1 0 100.00 100.00 0.5% down spread only srcclk1 from pll3 0 0 1 1 100.00 100.00 1% down spread only srcclk1 from pll3 0 1 0 0 100.00 100.00 1.5% down spread only srcclk1 from pll3 0 1 0 1 100.00 100.00 2% down spread only srcclk1 from pll3 0 1 1 0 100.00 100.00 2.5% down spread only srcclk1 from pll3 011 1 n/a n/a n/a n/a 1 0 0 0 24.576 24.576 none 24.576mhz on se1 and se2 1 0 0 1 24.576 98.304 none 24.576mhz on se1, 98.304mhz on se2 1 0 1 0 98.304 98.304 none 98.304mhz on se1 and se2 1 0 1 1 27.000 27.000 none 27mhz on se1 and se2 1 1 0 0 25.000 25.000 none 25mhz on se1 and se2 110 1 n/a n/a n/a n/a 111 0 n/a n/a n/a n/a 111 1 n/a n/a n/a n/a comment pll 3 disabled b1b1 b1b4 b1b3 b1b2 table 2: pll3 quick confi g uration fs l c 2 b0b7 fs l b 1 b0b6 fs l a 1 b0b5 cpu mhz src mhz pci mhz ref mhz u sb mhz dot mhz 0 0 0 266.66 0 0 1 133.33 0 1 0 200.00 0 1 1 166.66 1 0 0 333.33 1 0 1 100.00 1 1 0 400.00 111 1. fs l a and fs l b are low-threshold inputs.please see v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. also refer to the test clarification table. 2. fs l c is a three-level input. please see the v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. reserved 100.00 33.33 14.318 48.00 96.00 table 1: cpu fre q uenc y select table
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 17 datasheet table 3: io_vout select table b9b2 b9b1 b9b0 io_vout 000 0.3v 001 0.4v 010 0.5v 011 0.6v 100 0.7v 101 0.8v 110 0.9v 111 1.0v table 4: device id table 000 0 000 1 001 0 001 1 010 0 010 1 011 0 011 1 100 0 100 1 101 0 101 1 110 0 110 1 111 0 111 1 reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved 64 pin tssop/qfn b8b5 b8b4 comment 56 pin tssop/qfn b8b7 b8b6
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 18 datasheet pci_stop# power management smbus oe bit pci_stop# stop drive mode stoppable free running stoppable free running 1x running running running running 0 ck= high ck# = low running 1 ck= pull down ck# = low running disable xx cpu_stop# power management smbus oe bit pci_stop# sto p drive mode sto pp able free runnin g 1x running running 0 ck= high ck# = low running 1 ck= pull down ck# = low running disable xx cr# power management smbus oe bit cr# sto p drive mode sto pp able free runnin g 1 running running 0 disable x pd# power management device state w/o latched in p u t w/latched in p u t latches open power down m1 virtual power cycle to latches open single-ended clocks differential clocks (except cpu) low ck = pull down, ck# = low differential clocks differential clocks enable 0 low low enable 0 ck= pull down, ck# = low low enable ck= pull down, ck# = low x ck= pull down, ck# = low low hi-z single-ended clocks ck= pull down ck# = low ck= pull down ck# = low cpu1 ck= pull down, ck# = low ck= pull down, ck# = low ck= pull down, ck# = low running differential clocks (except cpu1) ck= pull down ck# = low
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 19 datasheet general smbus serial interface information for the ICS9LPR502 how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 20 datasheet byte 0 fs readback and pll selection register bit pin name description type default 7 - fslc cpu freq. sel. bit (most significant) r latch 6 - fslb cpu freq. sel. bit r latch 5 - fsla cpu fre q . sel. bit ( least si g nificant ) r latch 4- iamt_en set via smbus or dynamically by ck505 if detects dynamic m1 rw 0 3 reserved reserved rw 0 2 - src_main_sel select source for src main rw 0 1 - sata_sel select source for sata clock r w 0 0 - pd_restore 1 = on power down de-assert return to last known state 0 = clear all smbus configurations as if cold power-on and go to latches open state this bit is ignored and treated at '1' if device is in iamt mode. rw 1 byte 1 dot96 select and pll3 quick config register bit pin name description type default 7 13/14 src0_sel select src0 or dot96 r w 0 6 - pll1_ssc_sel select 0.5% down or center ssc r w 0 5 pll3_ssc_sel select 0.5% down or center ssc rw 0 4 pll3_cf3 pll3 quick config bit 3 rw 0 3 pll3_cf2 pll3 quick config bit 2 rw 0 2 pll3_cf1 pll3 quick confi g bit 1 r w 0 1 pll3_cf0 pll3 quick confi g bit 0 r w 1 0 pci_sel pci_sel rw 1 byte 2 output enable register bit pin name description type default 7 ref_oe output enable for ref, if disabled output is tri-stated rw 1 6 usb_oe output enable for usb rw 1 5 pcif5_oe output enable for pci5 rw 1 4 pci4_oe out p ut enable for pci4 r w 1 3 pci3_oe out p ut enable for pci3 r w 1 2 pci2_oe output enable for pci2 rw 1 1 pci1_oe output enable for pci1 rw 1 0 pci0_oe output enable for pci0 rw 1 byte 3 output enable register bit pin name description type default 7 src11_oe output enable for src11 rw 1 6 src10_oe output enable for src10 rw 1 5src9_oe out p ut enable for src9 r w 1 4 src8/itp_oe out p ut enable for src8 or itp r w 1 3 src7_oe output enable for src7 rw 1 2 src6_oe output enable for src6 rw 1 1src5_oe out p ut enable for src5 r w 1 0 src4_oe output enable for src4 rw 1 byte 4 output enable and spread spectrum disable register bit pin name description type default 7 src3_oe output enable for src3 rw 1 6 sata/src2_oe out p ut enable for sata/src2 r w 1 5src1_oe out p ut enable for src1 r w 1 4 src0/dot96_oe output enable for src0/dot96 rw 1 3 cpu1_oe output enable for cpu1 rw 1 2cpu0_oe out p ut enable for cpu0 r w 1 1 pll1_ssc_on enable pll1's s p read modulation r w 1 0 pll3_ssc_on enable pll3's spread modulation rw 1 s p read enabled 1 out p ut disabled s p read disabled s p read disabled output enabled out p ut enabled s p read enabled out p ut disabled out p ut disabled output disabled output disabled out p ut enabled out p ut enabled output enabled output enabled 0 01 output disabled out p ut disabled output enabled output enabled out p ut enabled out p ut enabled output enabled output enabled out p ut enabled out p ut enabled out p ut disabled output disabled output disabled out p ut disabled 1 output disabled output disabled out p ut disabled out p ut disabled output enabled output enabled output enabled out p ut enabled out p ut enabled output enabled output enabled out p ut enabled out p ut disabled out p ut disabled output disabled output disabled 0 output disabled output disabled output disabled 0 down s p read down spread see table 2: pll3 quick configuration only applies if byte 0, bit 2 = 0. dot96 center s p read center spread src0 01 1 sata = src_main configuration not saved iamt enabled src main = pll3 see table 1 : cpu frequency select table legacy mode src main = pll1 configuration saved sata = pll2 pci from pll1 pci from src_main
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 21 datasheet byte 5 clock request enable/configuration register bit pin name description type default 7 cr#_a_en enable cr#_a (clk req), pci0_oe must be = 1 for this bit to take effect rw 0 6 cr#_a_sel sets cr#_a to control either src0 or src2 rw 0 5 cr#_b_en enable cr#_b ( clk re q) rw 0 4 cr#_b_sel sets cr#_b -> src1 or src4 rw 0 3 cr#_c_en enable cr#_c ( clk re q) rw 0 2 cr#_c_sel sets cr#_c -> src0 or src2 rw 0 1 cr#_d_en enable cr#_d ( clk re q) rw 0 0 cr#_d_sel sets cr#_d -> src1 or src4 rw 0 byte 6 clock request enable/configuration and stop control register bit pin name description type default 7 cr#_e_en enable cr#_e ( clk re q) -> src6 rw 0 6cr#_f_en enable cr#_f ( clk re q) -> src8 rw 0 5 cr#_g_en enable cr#_g ( clk re q) -> src9 rw 0 4 cr#_h_en enable cr#_h ( clk re q) -> src10 rw 0 3 reserved reserved rw 0 2 reserved reserved rw 0 1 sscd_stp_crtl ( src1 ) if set, sscd (src1) stops with pci_stop# rw 0 0 src_stp_crtl if set, srcs (except src1) stop with pci_stop# rw 0 byte 7 vendor id/ revision id bit pin name description type default 7 rev code bit 3 r x 6 rev code bit 2 r x 5 rev code bit 1 r x 4 rev code bit 0 r x 3 vendor id bit 3 r 0 2 vendor id bit 2 r 0 1 vendor id bit 1 r 0 0 vendor id bit 0 r 1 byte 8 device id and output enable register bit pin name description type default 7 device_id3 r 0 6 device_id2 r 0 5 device_id1 r 0 4 device_id0 r 0 3 reserved reserved rw 0 2 reserved reserved rw 0 1 se1_oe output enable for se1 rw 0 0 se2_oe output enable for se2 rw 0 byte 9 output control register bit pin name description type default 7 pcif5 stop en allows control of pcif5 with assertion of pci_stop# rw 0 6 tme_readback truested mode enable ( tme ) stra p status r 0 5 reserved reserved rw 1 4 test mode select allows test select, i g nores ref/fsc/testsel rw 0 3 test mode entr y allows entr y into test mode, i g nores fsb/testmode rw 0 2 io_vout2 io out p ut volta g e select ( most si g nificant bit ) rw 1 1 io_vout1 io out p ut volta g e select rw 0 0 io_vout0 io output voltage select (least significant bit) rw 1 01 see table 3: v_io selection (default is 0.8v) test mode free running normal operation outputs hi-z - stops with pci_stop# assertion no overclocking - outputs = ref/n enable cr#_e 1 01 enable cr#_h enable cr#_g enable cr#_f stops with pci_stop# assertion free running stops with pci_stop# assertion disable cr#_h free running 0 disable cr#_e disable cr#_f disable cr#_g disable cr#_d cr#_d -> src1 enable cr#_a cr#_a -> src2 enable cr#_b cr#_b -> src4 enable cr#_c cr#_c -> src2 enable cr#_d cr#_d -> src4 disable cr#_b cr#_b -> src1 disable cr#_c cr#_c -> src0 disable cr#_a cr#_a -> src0 01 table of device identifier codes, used for differentiating between ck505 package options, etc. see device id table - - disabled - - revision id vendor specific 01 vendor id ics is 0001, binary enabled enabled normal operation disabled
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 22 datasheet byte 10 ck505 rev 0.85 functions (ics rev h silicon and higher) bit pin name description type default 7 src5_en readback readback of src5 enable latch r latch 6 reserved rw 0 5 reserved rw 0 4 reserved rw 0 3 reserved rw 0 2 reserved rw 0 1 cpu 1 stop enable enables control of cpu1 with cpu_stop# rw 1 0 cpu 0 stop enable enables control of cpu 0 with cpu_stop# rw 1 byte 11 ck505 rev 1.0 functions (ics rev p silicon and higher) bit pin name description type default 7 reserved rw 0 6 reserved rw 0 5 reserved rw 0 4 reserved rw 0 3 cpu2_iamt_en enables cpu2(itp) output in iamt state (m1) rw 0 2 cpu1_iamt_en enables cpu1 output in iamt state (m1) rw 1 1 pcie-gen2 pcie-gen2 status r 0 0 cpu2 stop enable enables control of cpu2(itp) with cpu_stop# rw 1 byte 12 byte count register bit pin name description type default 7 reserved rw 0 6 reserved rw 0 5 bc5 rw 0 4 bc4 rw 0 3 bc3 rw 1 2 bc2 rw 1 1 bc1 rw 0 0 bc0 rw 1 byte 13 ck505 pll1 m/n programming register bit pin name description type default 7 n div8 n divider 8 rw x 6 n div9 n divider 9 rw x 5 m div5 rw x 4 m div4 rw x 3 m div3 rw x 2 m div2 rw x 1 m div1 rw x 0 m div0 rw x byte 14 ck505 pll1 m/n programming register bit pin name description type default 7 n div7 rw x 6 n div6 rw x 5 n div5 rw x 4 n div4 rw x 3 n div3 rw x 2 n div2 rw x 1 n div1 rw x 0 n div0 rw x reserved - - - - - - - - - - - - - - - - 01 - - - - - - - - - - - 01 - - stoppable 01 off in iamt non-gen2 free runnin g tbd tbd tbd tbd free runnin g in iamt free runnin g in iamt pcie gen2 compliant tbd tbd tbd off in iamt stoppable 01 tbd tbd free running free runnin g src5 enabled tbd tbd tbd tbd tbd stoppable tbd tbd tbd tbd 01 cpu/pci stop enabled the decimal representation of m and n divider in byte 13 and 14 will configure the vco frequency. default at power up = latch-in or byte 0 rom table. - - - the decimal representation of m and n divider in byte 13 and 14 will configure the vco frequency. default at power up = latch-in or byte 0 rom table. read back byte count register, max bytes = 32 reserved
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 23 datasheet byte 15 ck505 pll1 spread spectrum control register bit pin name description type default 7 ssp7 rw x 6 ssp6 rw x 5 ssp5 rw x 4 ssp4 rw x 3 ssp3 rw x 2 ssp2 rw x 1 ssp1 rw x 0 ssp0 rw x byte 16 ck505 pll1 spread spectrum control register bit pin name description type default 7 reserved reserved rw 0 6 ssp14 rw x 5 ssp13 rw x 4 ssp12 rw x 3 ssp11 rw x 2 ssp10 rw x 1 ssp9 rw x 0 ssp8 rw x byte 17 ck505 pll3 m/n programming register bit pin name description type default 7 n div8 n divider 8 rw x 6 n div9 n divider 9 rw x 5 m div5 rw x 4 m div4 rw x 3 m div3 rw x 2 m div2 rw x 1 m div1 rw x 0 m div0 rw x byte 18 ck505 pll3 m/n programming register bit pin name description type default 7 n div7 rw x 6 n div6 rw x 5 n div5 rw x 4 n div4 rw x 3 n div3 rw x 2 n div2 rw x 1 n div1 rw x 0 n div0 rw x byte 19 ck505 pll3 spread spectrum control register bit pin name description type default 7 ssp7 rw x 6 ssp6 rw x 5 ssp5 rw x 4 ssp4 rw x 3 ssp3 rw x 2 ssp2 rw x 1 ssp1 rw x 0 ssp0 rw x 1 - - - - - - - - - - - - - - 01 - - - - - - - - - - - - - - - - 01 - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - 01 - - - - - - - - - - - - - - - 01 - the decimal representation of m and n divider in byte 17 and 18 will configure the vco frequency. default at power up = latch-in or byte 0 rom table. these spread spectrum bits will program the spread pecentage. contact ics for the correct values. these spread spectrum bits will program the spread pecentage. contact ics for the correct values. these spread spectrum bits will program the spread pecentage. contact ics for the correct values. the decimal representation of m and n divider in byte 17 and 18 will configure the vco frequency. default at power up = latch-in or byte 0 rom table.
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 24 datasheet byte 20 ck505 pll3 spread spectrum control register bit pin name description type default 7 reserved reserved rw 0 6 ssp14 rw x 5 ssp13 rw x 4 ssp12 rw x 3 ssp11 rw x 2 ssp10 rw x 1 ssp9 rw x 0 ssp8 rw x byte 21 m/n enables bit pin name description type default 7 reserved rw 0 6 reserved rw 0 5 reserved rw 0 4 reserved rw 0 3 reserved rw 0 2 reserved rw 0 1 m/n enable cpu rw 0 0 m/n enable rw 0 byte 22 cpu m/n programming bit pin na me description type default 7 n div bit 8 pll 1 m/n programming rw x 6 n div bit 9 (intel pll1 cpu) rw x 5m div bit 5 rw x 4m div bit 4 rw x 3m div bit 3 rw x 2m div bit 2 rw x 1m div bit 1 rw x 0m div bit 0 rw x byte 23 cpu m/n programming bit pin na me description type default 7 n div bit 7 pll 1 m/n programming rw x 6 n div bit 6 (intel pll1 cpu) rw x 5 n div bit 5 rw x 4 n div bit 4 rw x 3 n div bit 3 rw x 2 n div bit 2 rw x 1 n div bit 1 rw x 0n div bit 0 rw x bytes 24-62 reserved byte 63 special power management features (rev p silicon and higher) bit pin name description rw default 7 reserved rw 0 6 reserved rw 0 5 reserved rw 0 4 reserved rw 0 3 reserved rw 0 2 reserved rw 0 1 sata pll power management feature rw note 0 xtal pd control controls xtal on/off in legacy pd rw 1 *accessing any smbus bytes not shown in the datasheet could result in incorrect clock functions. off on off on note: default is "off" for rev p silicon and higher. 01 - - - 1 - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - disable enable 01 disable enable 01 - - - - - - - - - - - - - - 01 -- these spread spectrum bits will program the spread pecentage. contact ics for the correct values.
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 25 datasheet test clarification table comments fslc/ test_sel hw pin fslb/ test_mod e hw pin test entry bit b9b3 ref/n or hi-z b9b4 output <2.0v x 0 0 normal >2.0v 0 x 0 hi-z >2.0v 0 x 1 ref/n >2.0v 1 x 0 ref/n >2.0v 1 x 1 ref/n <2.0v x 1 0 hi-z <2.0v x 1 1 ref/n b9b3: 1= enter test mode, default = 0 (normal operation) b9b4: 1= ref/n, default = 0 (hi-z) hw s w power-up w/ test_sel = 1 to enter test mode cycle power to disable test mode fslc./test_sel -->3-level latched input if power-up w/ v>2.0v then use test_sel if power-up w/ v<2.0v then use fslc fslb/test_mode -->low vth input test_mode is a real time input if test_sel hw pin is 0 during power-up, test mode can be invoked through b9b3. if test mode is invoked by b9b3, only b9b4 is used to select hi-z or ref/n fslb/test_mode pin is not used. cycle power to disable test mode, one shot control
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 26 datasheet ordering information 9lpr502 y flft example: designation for tape and reel packaging lead free, rohs compliant (optional) package type f = ssop revision designator (will not correlate with datasheet revision) device type xxxx y f lf t min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n 0 8 0 8 variations min max min max 56 18.31 18.55 .720 .730 10-0034 reference doc.: jedec publication 95, mo-118 56-lead, 300 mil body, 25 mil, ssop n see variations see variations d mm. d ( inch ) symbol see variations see variations 0.635 basic 0.025 basic common dimensions in millimeters in inches common dimensions
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 27 datasheet index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c ordering information 9lpr502 y glft example: designation for tape and reel packaging lead free, rohs compliant package type g = tssop revision designator (will not correlate with datasheet revision) device type xxxx y g lf t min max min max a--1.20--.047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 56 13.90 14.10 .547 .555 10 - 0 0 3 9 n d mm. d (inch) reference doc.: jedec publication 95, m o-153 0.50 basic 0.020 basic see variations see variations see variations see variations 8.10 basic 0.319 basic 56-lead 6.10 mm. bod y , 0.50 mm. pitch tssop ( 240 mil ) ( 20 mil ) symbol in millimeters in inches common dimensions common dimensions
idt tm /ics tm 56-pin ck505 w/fully integrated voltage regulator 1124d?02/26/09 advance information ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator 28 datasheet e top view or anvil singulation a3 l n (ref.) e e e e (ref. ) (ref. ) (ref. ) (typ.) if a1 even e2 d2 d2 2 a c 0.08 c e2 2 2 2 1 sawn singulation index area seating plane are even thermal base odd b (n - 1)x n 1 chamfer 4x 0.6 x 0.6 max optional d d & & n d n d n e n e & n d n e (n - 1)x e ordering information 9lpr502 y klft example: designation for tape and reel packaging lead free, rohs compliant package type k = mlf revision designator (will not correlate with datasheet revision) device type xxxx y k lf t dimensions symbol min. max. a0.81.0 a1 0 0.05 n 56 a3 n d 14 b 0.18 0.3 n e 14 e d x e basic 8.00 x 8.00 d2 min. / max. 4.35 / 4.65 e2 min. / max. 5.05 / 5.35 l min. / max. 0.30 / 0.50 ics 56l tolerance symbol 0.50 basic dimensions 0.25 reference thermally enhanced, very thin, fine pitch quad flat / no lead plastic package
29 innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa tm ICS9LPR502 56-pin ck505 w/fully integrated voltage regulator datasheet revision history rev. issue date description page # a 2/19/2008 1. updated table 3: pll3 configuration. 2. release to final. 16 b 2/9/2009 1. updated electrical tables various c 2/23/2009 updated note under byte 63 table. 24 d 2/26/2009 updated byte 8 table. 21

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